L1 Cache Eviction Corrupting DDR on A9

Hi All! I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU. I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table...
Cache Maintenance Transactions

Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...
How to handle Cache flush in ACE?

Hi, I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache? Can anyone please help. Regards, Taniya...
chi protocol

can any1 explain me completion response and ordering in chi protocol??? and any good and easy source to understand chi protocol except spec..????
AHB protocol

I am newly learning AHBprotocol i just want to know what is meaning of single cycle bus master handover?