• Can a simple processor with load-store architecture support BURST?
    Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture...
  • Ahb
    why okay response is single cycle?but error,split,retry is two cycle.why?
  • AMBA AHB
    1)what are the different generations in AMBA AHB?
  • Does AHB-Lite Protocol require the master processor to be pipelined?
    The transfers in AHB protocols occur in two phases - address phase and data phase. Does this mean that the processor (Master) must have pipelined architecture?
  • AHB WRAP4 transfer
    Hi sir, I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave...