AXI3 write data interleaving with same AWID

This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple...
AXI locked access

Note: This was originally posted on 29th May 2008 at http://forums.arm.com Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a...
Write transfer in AXI3

A master wants to initiate write transfers to two different slaves whose address ranges are consequtive can he choose to initiate write transfer starting in 1st slave address range and choose ASIZE and...
Sampling on positive edge of clock of slave in AXI3

How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
Difference btw AXI3 and AXI4

Hi All , Can anyone please tell the difference btw AXI3 and AXI4. Regards Muthuvenkatesh