AXI4-lite :Wready dependency on Awvalid and Wvalid

In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals. Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals. ...
In case of AXI4 lite protocol,what is the relation between BValid signal and Wvalid signal?

In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?
why we need write strobe in axi

why we need write strobe signal in axi where we generate in our verif env Thanks
AXI-lite tlast signal missing and tready behavioral

Dear Forum, Can someone please clarify my 2 questions: a) Why in AXI lite protocol there is no tlast port? Mainly AXI lite consists of AXI-stream protocols, but there is no tlast port...
AXI write strobes

Note: This was originally posted on 21st February 2007 at http://forums.arm.com the AXI spec says: 10.1 About unaligned transfers [...] For any burst that is made up of data transfers wider than one byte...