AMBA AXI reset

According to spec IHI0022D_amba_axi_protocol_spec section A2.1 page number: A2-28 "All signals are sampled on the rising edge of the global clock " Q) Should RESET_N also be sampled on the rising...
AXI transfer

Consider Data interface is 64 bit. It is Write transfer. AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios. Scenario...
applications of amba axi

Note: This was originally posted on 7th February 2007 at http://forums.arm.com hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used...
AMBA AXI Write response

I am just going through the specs of AMBA AXI. I've few questions.It will be great if anybody clarify 1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response...
AMBA AXI CACHE

i am not able to understand working of this CACHE signal pleas explain with simple example. thank you!