GICv2 deactivation feature.

Hello all, There is one thing which is unclear for me in GICv2. GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a...
GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs

The GICv2's documentation describes as a programming error (see 5.2.4) having two or more copies of the same interrupt in the List registers . The notion of "same interrupt" is a bit vague when it comes...
Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects

Using the GICv2, software can change the CPU interfaces targeted by an interrupt (more precisely, an SPI) by writing to the corresponding GICD_ITARGETSR. The GICv2 specification states, in the paragraph...
Interrupt Routing flow in GICv3

Hi all, GIC is quite an interesting topic and interrupt controller can also be said as an most important module in an SoC that routes interrupts to the Processor. We know that there different interrupt...
GIC virtualization -- GICH_ELRSR and hardware interrupts

Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR). According to the GICv{2,3,4} specification, after the virtual machine has taken...