GICv2 deactivation feature.

Hello all, There is one thing which is unclear for me in GICv2. GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a...
Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects

Using the GICv2, software can change the CPU interfaces targeted by an interrupt (more precisely, an SPI) by writing to the corresponding GICD_ITARGETSR. The GICv2 specification states, in the paragraph...
why the inter-core SGI interrupt cannot be trigged on GICv3 hardware

My hareware environment: 1. a ARMv8 processor , which runs in 64bit EL3 and 32bit EL2&EL1. 2. a GICv3 interrupt controller Running in 32bit hyp mode, I try to send a SGI interrupt from core0 to core1...
GICv2 How to resolve Multiple Interrupt appearing on a CPU

Hi All, I am facing issue where, in the event of multiple interrupts on GIC in close vicinity, I am unable to decide on which interrupt has been asserted, to service them properly. Details:- This...
What will happen if one core sends SGI interrupt to another core quickly and continuously？

I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1 It seems that ARM does not provide guidance in...