ARMv8 Exception level on Startup

Hi, When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported? How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate...
How interrupts are routed in EL3/EL2/EL1 mode

Sorry for basic question, For ARM64, we have different interrupt vector table for each mode EL3/EL2/EL1 I am wondering, how a specific IRQ is routed to given mode. in GIC, I am not able to find...
D-Cache read problem in EL2 mode ARM V8

Hello, I am working on EL2 mode ARM V8 , Problem I am facing when I enable D-cache then I am not able to read the data. My boot flow is EL3 to EL2 and in EL2 snippet of code is below 1 stp x29...
Comparing ARM Cortex-A72 and ARM Cortex-A57

The latest high-performance ARMv8-A processor is the Cortex-A72 .The press release reports that the A72 delivers CPU performance that is 50x greater than leading smartphones from five years ago and will...
Cycle Accurate ARM Cortex-A53 and Cortex-A57 Models Support AArch64

We ( The specified item was not found. ) have just completed our first major release of 2014. It includes significant new content and many bug fixes to all products. Today, I would like to highlight the...