ACE protocol : Eviction and snoop request at same time

How to handle below scenario ? At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high) At same time t1...
Cache in SOCs

Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
Turning on MMU and caches on Cortex-A7?

In my little program (rpi_stub) it's time to turn on MMU and caches. Most of it I seem to have hold of, except cache invalidations. In multicore situation (rpi_doesn't support yet, but maybe later...
ARMv8-64 Cache management in a PSCI functions

Hi everyone, I'm currently working on type-1 hypervisor and would like to provide support of the ARM Power State Coordination Interface. http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D...
Cache Maintenance Transactions

Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...