GIC-v3&4: Regarding the Acknowledge Register

Hi all, I need some clarification related to acknowledge register in GICv3&4 document. ----------------------------------------------------------------------------------------------------------------...
GIC-400 non-secure access

Hi, experts I'm the new one porting armv8 linux. I have some problem about gic400 access. In the porting linux progress,CPU will switch to EL1NS. In gic_dist_init() function, I read the the GICD_ISENABLERn...
GIC virtualization -- GICH_ELRSR and hardware interrupts

Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR). According to the GICv{2,3,4} specification, after the virtual machine has taken...
The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?

In the the arm gic arch specification (version 2) section 3.9.2, it has been given that for any implementation of GICv2 (with or without Security Extn) we can configure the GIC to generate FIQ for...
GIC 500 :: Not able to find the definition for GICD_IROUTERn register

Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.