GIC v3&4: Programming sequence of GIC Registers

Hi., Is there any sequence in programming GIC Registers. Physical Interrupts point of view, I have followed sequence as follows: GICD GICR GICC/ICC Coming to Virtual Interrupts point of view, I had small...
GIC-400 non-secure access

Hi, experts I'm the new one porting armv8 linux. I have some problem about gic400 access. In the porting linux progress,CPU will switch to EL1NS. In gic_dist_init() function, I read the the GICD_ISENABLERn...
GIC virtualization -- GICH_ELRSR and hardware interrupts

Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR). According to the GICv{2,3,4} specification, after the virtual machine has taken...
The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?

In the the arm gic arch specification (version 2) section 3.9.2, it has been given that for any implementation of GICv2 (with or without Security Extn) we can configure the GIC to generate FIQ for...
What will happen if one core sends SGI interrupt to another core quickly and continuously？

I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1 It seems that ARM does not provide guidance in...