What's wrong when watchpoint doesn't watch?

I've been trying to get a watchpoint to trigger, but no luck. There should be 4 watchpoints accordíng to DBGDIDR, DBGDSCR=0x0204000e, so there shouldn't be any problems there? I use (just in case) the...
How to access the memory mapped debug registers?

Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR...
Unable to set software breakpoints in IAR IDE

I'm using IAR Embedded Workbench to debug a Cortex-M0 system interfaced through ST-LINK/V2 SWD. The processor isn't officially supported because it is under development, but the configuration files...
Cortex-A7 instruction lists

Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net). They are generated from ARMv7-A/R ARM with a simple AWK-script and then...
by which instruction the secondary core is triggered while starting the secondary cpu

the booting of seconday cpu is initiated by the primary core. and some work is completed on the primary cpu and some is completed on the secondary cpu to complete the hotplug operation for cpu_up. I am...