Cache in SOCs

Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
What flow should I execute to make cache and MMU work properly when I turn into non secure world?

In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world. But the most confusing thing is that what...
L1 Cache Eviction Corrupting DDR on A9

Hi All! I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU. I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table...
ARMv8-64 Cache management in a PSCI functions

Hi everyone, I'm currently working on type-1 hypervisor and would like to provide support of the ARM Power State Coordination Interface. http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D...
Cache Maintenance Transactions

Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...