Weird SPSR behaviour

I was trying to write a register context saving/restoring when I came across a weird behaviour. My code (sorry, tried to format tens of times, but the editor WANTS to make asm a table): asm volatile ...
How to access the memory mapped debug registers?

Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR...
Issue in writing a data in PMU register

Hi, Following are the query regarding the ARM Cortex A7 MP Core. In ARM Cortex A7 MP Core,facing a issue in memory mapping the registers and accessing the registers by read and write operations. By means...
Cortex-A7 instruction lists

Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net). They are generated from ARMv7-A/R ARM with a simple AWK-script and then...
Arm alignment: all ARM processor requrie 4 bytes alignment for SP?

It seems Arm9 requries, but A7 doesn't.