• LDR Instruction
    Note: This was originally posted on 5th November 2008 at http://forums.arm.com Hi all,         I am new to the thumb-2 instruction set. In one of my sample code I noticed a instruction          LDR r0...
  • ARM/THUMB instructions that change execution path?
    Has anybody come across a list of ARM & THUMB instructions that cause deviation from the linear instruction stream? I've been trying to figure out gdb-stub single stepping using software interrupts, and...
  • Hazard conditions in CHI
    In chapter 4.9.2 At the ICN(HN-F) node CHI specification talks about what ICN should do when there is hazard condition. It says: One example of these rules is chapter 5.6.1 CopyBack-Snoop hazard...
  • Cortex-A7 instruction lists
    Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net). They are generated from ARMv7-A/R ARM with a simple AWK-script and then...
  • How to understand Exclusive Transaction failure conditions in CHI?
    The purpose of Exclusive Access is to read, calculate and modify a cache line atomically. The built-in Atomic Transactions can do some basic calculations at ICN or SN, but if more complex operations are...