How to handle clean operation in Data Cache

Hi, I have a question. when a processor sends a clean request to data cache, how data cache should behave? 1. does it need to evict all cache lines present in cache (including clean lines) or does...
ACE5 / ACE5 Lite questions for ARBAR/AWBAR, AWSTASH*, and BROADCAST* signals

Hi, 1) ARBAR/AWBAR These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. ...
ACE-Lite

Hi, Can we develop the VIP of ace-lite without developing the ace. Like for ace-lite VIP development instead of taking two ace masters and one ace-lite master can we take only three ace-lite masters...
Further explanation needed for VAxQOSACCEPT, AWAKEUP, ACWAKEUP and SYSO*

Hi ARM/arktos, Seems like this online discussion is not working properly. I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email. So most likely you...
AXI read transfer

If the slave is not able to process read request from master, which response is expected from slave?