Exception handlers and interrupt

Hi All, i went through this link http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html and related a53 vector table implementation. in this regard, i have a question...
Turning on MMU and caches on Cortex-A7?

In my little program (rpi_stub) it's time to turn on MMU and caches. Most of it I seem to have hold of, except cache invalidations. In multicore situation (rpi_doesn't support yet, but maybe later...
ARM instruction set pseudo instructions

Does anyone know if there is a list of ARM instruction set pseudo instructions? Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and another list...
Booting sama5d2 with lpddr2

I'm having a SAMA5D26C with a LPDDR2 EDB1332BDBH-1. The CPU boots successfully ROMBOOT and is able to load at91bootstrap from QSPI memory. I get debug output from at91bootstrap, but I fail to load linux...
Cortex-A7 instruction lists

Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net). They are generated from ARMv7-A/R ARM with a simple AWK-script and then...