How to handle Cache flush in ACE?

Hi, I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache? Can anyone please help. Regards, Taniya...
How can I use imx6 in Asymmetric (***) mode?

I would like to use iMX6 in asymmetric mode (Windows EC7 + Linux). Is that anyhow possible? Marco
How to invalidate cache (NVIDIA Drive PX2, ARMv8)

Hey, on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2 . Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With...
L1 Cache Eviction Corrupting DDR on A9

Hi All! I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU. I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table...
Address Space Layout Randomization

System optimization involves running Linux applications and understanding the impact on the hardware and other software in a system. It would be great if system optimization could be done by running benchmarks...