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    This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and...
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    Hey I have some digital inputs which I wanted to convert it into analog signals and send it to Industrial Valve to control the flow of water but because of not familiar with digital to analog conversion...
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    What are valid transactions after an SWD line reset for SWDv0? This is in reference to section 4.4.3 of ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
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    My son has had asthma since he was three years old. Ben is now 10, and during that time, it’s been fascinating to experience the challenges associated with asthma technique and medication from a parent...
  • CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...