• GICv3 -- accessing the redistributors of other cores
    In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores...
  • IoT basics, possible projects?
    Hello, I'm sorry for asking such a generic question but I have been reading up about this for the past week or so and haven't really gotten anywhere. I'm an embedded developer working with ARM and AVR...
  • Embedded World 2015 - More than The Internet of Things
    The ARM team have just come back from another successful Embedded World . For those who aren’t familiar, Embedded World is the biggest embedded trade show, attracting exhibitors and visitors from across...
  • 7 inch TFT image not good for sample code
    Hi I have made images to be visible in TFT using sample codes from github for nuvoton I am using N9H30 series evaluation board,In this series I have dumped only sample code but that image is also...
  • Is there any scenario where HWDATA and HRDATA are used simultaneously?
    I couldnt find any examples as such, as far as I've seen, the two data in the busses HWDATA and HRDATA are never used at the same time as other. Is there any scenario where in one time cycle, the HWDATA...