HREADY signal and single transfer in ahb lite

HI... A) 1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH. 2).First thing i complete the first transfer...
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...
State Machine for AHB-Lite Protocol

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and...
Relation between Hsel and Hready in AMBA AHB

Hi, In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase...