GICv3 -- accessing the redistributors of other cores

In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores...
Other core's view after writing ICC_SGI1R_EL1 to trigger SGI

For example, the codes are executed in core0. codes: (1) send SGI to core1 ICC_SGI1R_EL1 (2) set(a) = 1 i) Then the core1 will first see the irq or the change of variable a? ii) If I add ISB...
by which instruction the secondary core is triggered while starting the secondary cpu

the booting of seconday cpu is initiated by the primary core. and some work is completed on the primary cpu and some is completed on the secondary cpu to complete the hotplug operation for cpu_up. I am...
Cortex A9 dual core - How to achieve an AMP system without an RTOS?

One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end image analysis task). Due to cost or other over...
Regarding implementation of a scenario in AHB protocol

Hi, While implementing AHB protocol, I am stuck at a scenario handling. I am handling early burst termination with undefined length INCR burst for remaining beats. Scenario : if a WRAP16 type burst...