Write Data Interleaving - AXI

Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hello, Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec...
Removal of WID's in AMBA AXI4

Hi , What is the purpose of removing ID's (WID) in AXI4 ? If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please...
AXI4 Burst Transactions

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...
Why AXI4 changed the definition of AxCACHE?

Hi, In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate. But is there any concrete reason for this change? Actually...
AXI4

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this? What is the meaning of bandwidth in this context? What are the values of bandwidth...