TCP/IP stack for Cortex-A9 MPCore

Hi, I'm currently working on a project based on the Arria V SoC FPGA (ARM Cortex-A9 MPCore). The goal of this project is to run a high speed ethernet link. For some reasons the customer don't want to...
Cortex A9 dual core - How to achieve an AMP system without an RTOS?

One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end image analysis task). Due to cost or other over...
How to find the right development board for your Kickstarter (or any design)

For our first interview during Kickstarter Week we decided to start at the beginning of hardware design and look at the development board choices for aspiring Kickstarters. This is a good news scenario...
AMP system on Cortex-A9. How to do it?

Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic...
Converting virtual address of Instruction fault address register to physical address in cotex A9

Content of IFAR=0xaa4e8ef0 IFSR=0x0000000d DFSR:0x00000000 DFAR:0x00004000 How to find Physical address form this?