What use of 'AL condition' in ARM IT block?

Hi, I read the following on IT block in ARM Thumb2 instruction. I don't understand the last sentence on AL to get the changed behavior. Could you explain it to me? Thanks, ///////////// A8.6.50 IT If...
ARM/THUMB instructions that change execution path?

Has anybody come across a list of ARM & THUMB instructions that cause deviation from the linear instruction stream? I've been trying to figure out gdb-stub single stepping using software interrupts, and...
[Cortex M0] Number of clock cycles for LDR instruction

Hello, I need to know the exact number of the clock cycles per each instruction in terms of the system clock frequency especially the "LDR" instruction Here is the needed instruction: "LDR r3,[r1...
Cortex-A7 instruction lists

Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net). They are generated from ARMv7-A/R ARM with a simple AWK-script and then...
Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and...