• AXI4 Burst Transactions
    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...
  • AXI4 - read data interleaving
    Hi Folks, We need a clarification on Read Data Interleaving on AXI4 Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed...
  • Why AXI4 changed the definition of AxCACHE?
    Hi, In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate. But is there any concrete reason for this change? Actually...
  • AXI4
    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this? What is the meaning of bandwidth in this context? What are the values of bandwidth...
  • WID not present in AXI4
    can you clarify to me, why there is no WID in AXI4?