CHI protocol cache line states

The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...
Cache Maintenance Transactions

Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...
How to map tag RAM banks to data cache lines in Cortex-R5?

Hi, We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data...
How to handle Cache flush in ACE?

Hi, I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache? Can anyone please help. Regards, Taniya...
AMBA AXI CACHE

i am not able to understand working of this CACHE signal pleas explain with simple example. thank you!