MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

Hi, Facing the issue: "MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave" Here is the Inputs: We are using the custom SOC, in which we are testing...
AHB WRAP4 transfer

Hi sir, I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave...
AHB split retry response

Note: This was originally posted on 9th December 2008 at http://forums.arm.com IN AMBA AHB , there are split and retry response. These are 2 cycle responses. whole SPLIT sequence is given in the spec...
Ahb

why okay response is single cycle?but error,split,retry is two cycle.why?
Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...