GICv2 How to resolve Multiple Interrupt appearing on a CPU

Hi All, I am facing issue where, in the event of multiple interrupts on GIC in close vicinity, I am unable to decide on which interrupt has been asserted, to service them properly. Details:- This...
GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs

The GICv2's documentation describes as a programming error (see 5.2.4) having two or more copies of the same interrupt in the List registers . The notion of "same interrupt" is a bit vague when it comes...
Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects

Using the GICv2, software can change the CPU interfaces targeted by an interrupt (more precisely, an SPI) by writing to the corresponding GICD_ITARGETSR. The GICv2 specification states, in the paragraph...
What will happen if one core sends SGI interrupt to another core quickly and continuously？

I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1 It seems that ARM does not provide guidance in...
Interrupt Routing flow in GICv3

Hi all, GIC is quite an interesting topic and interrupt controller can also be said as an most important module in an SoC that routes interrupts to the Processor. We know that there different interrupt...