• Cortex-A9 core registers
    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...
  • Cortex-A15MP Core Registers
    Hi, I am using ARM v7-A (Cortex A15 MP) and i want to observe the stack context, as i understand it, there are some offset values inside of ARM Core Registers (between LP, SP and PC), and the offset...
  • Address of core register on M0+ core
    I have been looking for the actual address of the core register of an arm M0+ core. I got a little bit confused where they are actually located in the arm core address space. Thanks!
  • Cortex-m0 instructions and core registers immediete values
    Hi, i have just got a cortex-m0(LPC1114) based dev board. I'm reading about the architecture and instructions. My understanding is that it supports most thumb 16-bit instructions and a handful thumb-2...
  • Cortex A9 single core
    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...