• why descriptions of SAU_RLAR is different in two user duides?
    Hi I found a difference here: In arm_cortex_m33_dgug_100235_0100_01_en page:322 [0] ENABLE Enable. SAU region enable. The possible values of this bit are: 0 SAU region is enabled. 1 SAU region is...
  • Relocating the Vector table in Cortex - M0
    Hi I am having an issue, related to vector table relocation in a Cortex - m0 based device, as VTOR isnt available there in this core, how can i manage the ISRs in a application which is not at default...
  • Cortex M33 Tracing
    Hey, As I am exploring the tracing capabilities present in the Cortex M33, there are some things that I am not able to understand fully, such as the connection between ETM and the tracing sinks. As...
  • Does Cortex-M33/M35P support bit band?
    I will develop on cortex-M33 and M35P these days. I didn't find M35P's reference manual but I found that bit band is not referred in M33's reference manual. Because both of them are based on ARMv8-M,...
  • IMPRECISERR on Cortex-M33 r0p3
    Hi, I just wanted to double-check, that IMPRECISERR (BFSR part of CFSR register ) is by default not implemented in Cortex-M33 (as mentioned here ). The reason I am asking is that on a different page...