• Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?
    Hello guys, I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA. Is ARMv7-M3 instructions compatible to ARMv7-A, especially...
  • IOC flag at FPSCR register
    I using Cortex-R4. And I reading "Cortex™-R4 and Cortex-R4F Technical Reference Manual(Revision:r1p3)". In my system,  IOC flag in FPSCR register is set with unexpected processing. What is the condition...
  • Instruction and Related Flag update
    Hi all, When the arithmetic and logical instruction like SUBS, LSLS are executed the processor flag will be updated. Can somebody point to the document where the information on affected flags of each...
  • Is Thumb to ARM mode overhead
    Hi all, Consider high priority routines are executing in ARM mode and low priority in Thumb mode. There could be constant switching between ARM and THUMB mode. In this inter-working model is there any...
  • thumb 2 instruction set
    The thumb 2 instruction contains both the instruction sets( best of both worlds) ARM and THUMB. So my question is how does processor come to know that the fetched one is 16 bit size instruction...