• Cortex-M7 load instruction latency and pairing
    Hello, What is the latency for the LDR instruction when the result is used for integer arithmetic operations (for example DSP MAC instructions)? Also, can 64-bit loads (LDRD) be paired with another instruction...
  • Understanding XDMAC on Cortex-M7
    I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it...
  • A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors
    Introduction All experienced embedded system designers know that interrupt latency is one of the key characteristics of a microcontrolller, and are aware that this is crucial for many applications...
  • LDM/STM interruption of Cortex-M7.
    Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
  • STM32F103C6 doesn't receive the complete data thorugh i2c as a slave with interrupt enabled, mantains SCL low after first data byte
    I'm trying to send a dat from master to a slave (the STM32F103C6) with HAL function for polling mode is working well and it is receiving all the data I send (I got all ACKs) but when I try to do the...