[DS-5] Is it possible to set a watchpoint on a spec reg?

Hi Folks, I don't think it is possible but maybe you have any tricks... is it possible to set something along the watchpoint on the spec reg? I have a need at checking out on the accesses to scr_el3...
Hello, my question is about watchpoint.

When I set a on-chip breakpoint with MMU enabled, virtual address is 0xcc000000 ( real physical address is 0xbb000000)for example. Once the MMU map changed, when the breakpoint would be hit, new virtual...
Development with ARMv8a debug (and watchpoint) registers.

Hello folks, I have two simple questions related to the debug exceptions on ARMv8. I expect the debug related registers such as DBGWCR, DBGWVR, DBGBCR and DBGBVR to be common for all processor cores...
How to write to DHCSR register in Cortex-M

I want to make C_DEBUGEN (register DHCSR) zero. I tried this. (CoreDebug->DHCSR = (unsigned int)0xA05F0000;) But again, C_Debugen is set to 1. I want to know how to set it to 0. It is possible...
How to deice debug target exception level of watchpoint on ARMv8 architecture

Hello, everyone I'm new to this community. I'd like to ask many questions and want to help someone. Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme. I found...