ARMv8 mmu problem

Hi ARM experts, I have a problem in using armv8 mmu in bare-metal system: When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA. In Armv8 ARM page D4-1744...
Correct usage of the NSTable bit in aarch64/armv7a LPAE

I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that...
Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler

Hi There, I am writing some bootload code for the TI Sitara AM5726 processor which has Dual Arm-v7 Cortex-A15 cores. The uBoot bootloader is the code that runs before starting the Linux Kernel and is...
Precise abort vs synchronous abort in armv7

I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or...
Enable MMU and d-cache on ARMv8 for u-boot

Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...