Cortex A9 single core

From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
ARM Cortex A8 : Enabling D Cache aborts

I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
MMU and Cache configuration

Hello there, I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core. I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and...
Clean Whole Cache on Cortex-A9

I am doing some benchmarking and I need to clear the cache before each test. I have this example here: Caches and Self-Modifying Code However, I just want to clean the whole cache. Is there an easy way...
Disabling L2 cache for CPU1 (Zynq-7000)

Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...