Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...
Different between AF vs AP (MMU Setup)

What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
MMU attributes implications on memory bandwidth

Hello, I have a multi-core system which implements an L3 cache memory and a memory controller. In addition, i am using ARM Cortex-A72 MPcores, 2 cores per cluster, several clusters. I am trying...
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
Secure world memory access with MMU disabled

Hi, I am a newbie to the TrustZone architecture. I learned that, in secure world, whether a memory access is secure or not is determined by the NS field in the translation descriptor and, in non-secure...