• Exceptions levels in the ARMv8 architecture
    Hello There are four exceptions levels in the ARMv8 architecture. EL0 EL1 EL2 EL3 Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure...
  • Exception Level Switch in ARMv8
    HI there: i am developing on a ARMv8 a57 based CPU, i want to disable the cache mechanism. it seems i need the access the corresponding registers in EL1 or above. i wonder how could i switch the EL...
  • ARMv8-M - toolchains / virtual platforms
    Hello, I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so. 1. I need a toolchain that supports...
  • GIC-400 controller virtual interrupt handling in VM and hypervisor
    Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57. Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension Let assume...
  • Confusion about exception level of ARMv8
    Hi, I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8. 1. How...