What is the difference between PoC and PoU for Cortex-A7 MPCore?

hi, experts: ARM ARM manual introduces a concept PoC and PoU for cache maintanance operations. Based on Cortex-A7 MPCore TRM and ARM ARM manual, i got below conclusion: 1. PoC points to external DRAM...
Break Points and Watch Points

Greetings, Sir,i am working on SWD, after Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These...
Usage of gathering and reordering in the ARMv8

Hi all, Kindly suggest some logical code to realize the gathering and re-ordering attribute in the ARMv8. How this attribute can be best utilized for actual use case scenarios ?
how does ARMv8 switch to run application(EL0) from kernel(EL1)?

hi experts, I am studying the ARMv8 exception levels. I have a question about ELs. EL1 is described to run OS kernel and EL0 is application level. The exception levels change only occur on exception...
why some instructions are not required to be explicitly synchronized ?

Dear all: In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions , it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need...