GIC-400 controller virtual interrupt handling in VM and hypervisor

Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57. Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension Let assume...
Resetting GIC by SW?

Hello, we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500. The M3 has access to all registers that...
GIC order of completion of interrupts

Hello, Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of...
Virtual IRQ/FIQ exceptions with ARMv8 and no GIC

Hello All, I had a couple of clarifications w.r.t the ARMv8 docs and Virtual IRQ/FIQ exceptions in conjunction with HCR.{IMO,FMO} bits and interrupt routing. A) Does this mechanism require a GIC or can...
Cortex-A9/GIC: de-activate an active interrupt

Hi my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world. No...