ARM Cortex A9 flush cache

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...
Is it necessary to flush data cache of a modified page table entry?

Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
ARM PMU access DRAM Event

Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
ARM Cortex A8 L2 Cache Flush Invalidate

Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1"); asm volatile ("smc #1...
System wide cache flush

Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...