ARM Cortex A9 - Enabling/Disabling the Caches

Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
cortex A9 multi-core

I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.
Cortex-A9 core registers

In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...
De-merits in using Cortex A9 for single core processor

Hi Experts, A8 is meant for single core and A9 is for multi-core based. Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like...
Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

Hi I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core. Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled...