shareability attribute for armv8 cortex a-53

Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ?

Hello, I'm a student and I'm interested in how to compare ACPI Sleep States (Sx) and processor power states (Cx) with ARM Cortex-A states e.g. Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop...
Cache cleaning and invalidating in ARM Cortex-A

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...
VMSAv8-64 and spinlock

Hi, I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache...
How to flush write buffer when memory attribute is normal_nc

Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...