[Cortex-A53] Exception Syndrome Register - Exception Class

Hi, I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information. Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64...
Ways to Tx data from Cortex R5 to A53?

Hello, I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some...
armv7a/armv8 : Undefined Abort Exception and MMU

Hi ! When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before...
interrupt distribution on A53 processor

Hi, Linux Kernel 4.9 Processor a53 SMP 64 Bit linux image Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts. moving...
Cortex A53 Out of Order?

Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...