Multicore SMP using Linux kernel

Hi, I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary...
GICv2 initialization for Non-Secure World

Hi, Recently I am working on porting our Cortex A7 code that used to run in secure world to non-secure world for some reason. I got a problem when it came to GIC initialization. I noticed that in order...
L1 data cache and unified cache disabled in AMP mode for Cortex-a7

Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...
GIC order of completion of interrupts

Hello, Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of...
SMP ARM cores hang when using DMA and two cores enabled

Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...