Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?

Hi Fellows, I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction...
Does MSR DAIF require ISB instruction? If no, why?

Dear experts, I see a lot of code in opensource like .macro disable_daif msr daifset, #0xf .endm and it doesn't apply ISB instruction after it. Though I read in ARM manual that: "context-changing...
What is the difference of DMB and DSB instruction?

Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...
Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
Synchronization Between CortexA and CortexM

Hello, I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4). Currently, I use Load/Store executive assembly instructions along with memory attributes...