The merit of data cache cleaning

Hello everyone, my 1st question to the ARM community; please excuse my ignorance. Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9). To pass message...
ARMv7 CortexA9 Cache Policy - No allocate ?

I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

Hello, Consider following scenario: A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache. Now, the s/w writes...
ARM Cortex A8 L2 Cache Flush Invalidate

Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1"); asm volatile ("smc #1...
ARM Cortex A9 - Enabling/Disabling the Caches

Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...