Why does ARM Branch with Link (BL) instruction considers prefetch?

Hi, When I read the words below dot line, I don't understand why "R14 is adjusted to allow for the prefetch" Could you explain it to me? Thanks, ....... Branch with Link (BL) writes the old PC into the...
Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

Cortex-A7 pipeline is non-symmetric, what does this attribute mean? My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries...
What does "low interrupt latency" means

Hi All, In R4 trm, there are some words about low interrupt latency. I have a question about it. " Low interrupt latency On receipt of an interrupt, the processor abandons any pending restartable memory...
Question about a code snippet on ARM, Thumb state change

Hi, I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling. add R1,PC,#1 ;Load address of SUB_BRANCH...