• How to configure L2 cache in Cortex-A7
    Hi all, I am working on OrangePi board. The board configuration is, Quad-Core ARM Cortex-A7, 1.6 GHz 32 KB L1 I-Cache and 32 KB L1 D-Cache per core 512 KB L2-Cache I have few queries related...
  • MMU deactivation and I-Cache / Branch Predictor
    Hi ! In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible...
  • pc hangs in process of cache setup - Cortex-A7
    In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows:      1. Enable SMP bit and disable MMU.      2. Disable I cache in L1, and invalidate it , then enable...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Using the whole Cortex-A L2 Cache without external memory
    I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory. The CPU boots from an external 4MBytes SPI NOR FLASH chip. It has 512 KBytes...