• Cortex A9 single core
    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
  • Cortex-A7 pipeline is non-symmetric, what does this attribute mean?
    Cortex-A7 pipeline is non-symmetric, what does this attribute mean? My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries...
  • What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?
    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean? In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow: I want ask the in-order and out-of-order...
  • Efficient uasage of PLD instruction in combination with Load instructions?
    Hi all,  after a long time I'm back to forum with a question I'm posting this question with some pseudo code for(i=0;i<100;i++) { instruction1 instruction2 instruction3 ................. instructionA...
  • The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?
    The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean? I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock. But in...